1. Technical Field
This disclosure relates to a method of forming an insulation layer structure and a method of manufacturing a semiconductor device using the same and more particularly, to a method of forming an insulation layer structure having a recess portion at an upper central portion and a method of manufacturing a semiconductor device including an insulation layer structure having a recess portion at an upper central portion.
2. Description of the Related Art
Generally speaking, semiconductor memory devices may be classified either as volatile memory devices, such as random-access memory (RAM) devices, or non-volatile memory devices, such as read-only memory (ROM) devices. Volatile semiconductor memory devices have relatively high operation speeds for inputting data and outputting data, but may lose stored data as time elapses. Non-volatile semiconductor memory devices have relatively low operation speeds for inputting data and outputting data, but are capable of permanently storing data.
Presently, among non-volatile memory devices, electrically erasable programmable ROM (EEPROM) devices or flash memory devices have been much in demand. The flash memory device has a structure that electrically controls the input and output of data using a Fowler-Nordheim (F-N) tunneling mechanism or a channel hot electron injection mechanism.
In order to increase an integration degree of the semiconductor device, a critical dimension (CD) of a floating gate of the flash memory device has been significantly reduced, resulting in an increase in failures of the semiconductor device caused by increased misalignment defects or a decreased coupling ratio.
To reduce misalignment defects, a conductive layer may be self-aligned relative to an isolation layer pattern to form a floating gate by a self-aligned shallow trench isolation (SA-STI) process or a self-aligned polysilicon STI (SAP-STI) process. Furthermore, the floating gate may have an enlarged contact area to make contact with a dielectric layer formed on the floating gate, thereby augmenting the coupling ratio.
An example method of manufacturing the flash memory device by the SAP-STI process is disclosed in U.S. Pat. No. 6,465,293. According to this conventional SAP-STI process, only an upper face of the floating gate is exposed. The side faces of the floating gate are not exposed because the isolation layer is formed between the neighboring floating gates adjacent to each other. Thus, in order to increase an effective area of the dielectric layer, the isolation layer should be etched further away to partially expose the side surface of the floating gate.
However, when a small quantity of the isolation layer is removed, an exposure area of the side surface of the floating gate is negligible, so that the coupling ratio of the semiconductor device is not sufficiently improved. In contrast, when the isolation layer is excessively etched to thereby expose most of the side surface of the floating gate, a tunnel oxide layer beneath the floating gate may be removed from the substrate or significant damage may be caused to the tunnel oxide layer.
Therefore, although various techniques for improving the coupling ratio have been proposed, such as changes to the structures of the floating gate and the isolation layer, there is still a requirement for a method of improving the coupling ratio of a semiconductor device without damaging the tunnel oxide layer.
Embodiments of the invention address these and other disadvantages of the conventional art.